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19-3596; Rev 0; 2/05
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
General Description
The MAX6892/MAX6893/MAX6894 pin-selectable, multivoltage supply sequencers/supervisors monitor several voltage-detector inputs and one watchdog input, asserting the respective voltage detector or watchdog output when the inputs drop below the configured voltage thresholds or the watchdog timer expires. The MAX6892 features eight voltage detector inputs and 10 outputs. The MAX6893 features six voltage-detector inputs and eight outputs, while the MAX6894 features four voltage detector inputs and six outputs. A RESET output ensures all monitored inputs are above the set thresholds. The voltage detector outputs are configured as open drain. Manual reset and margin disable inputs offer additional flexibility. The thresholds of the MAX6892/MAX6893/MAX6894 are selected through five logic inputs (TH0-TH4). The logic on these five inputs selects the supply voltage tolerance (5% or 10%) and one of 32 factory-set thresholds settings. Watchdog and reset timeout periods can use factory default settings or are independently adjustable by connecting external capacitors. When any of the monitored voltages falls below its threshold, the respective output asserts and remains asserted for 6.25ms (typ) after the monitored voltage exceeds the threshold. The outputs can be connected to the shutdown or enable inputs of DC-DC regulators to provide turn-on power sequencing to ensure proper system initialization. The MAX6892 is available in a 5mm x 5mm x 0.8mm, 32-pin, thin QFN package, while the MAX6893/ MAX6894 are available in a 5mm x 5mm x 0.8mm, 28pin, thin QFN package. The MAX6892/MAX6893/ MAX6894 are specified to operate over the extended temperature range (-40C to +85C) Dedicated RESET and WDO Outputs Capacitor-Adjustable Reset and Watchdog Timeout Periods Factory-Default Reset and Watchdog Timeout Periods Up to Eight Independent, Open-Drain Power-Good Outputs Enable Margining Disable and Manual Reset Controls -40C to +85C Operating Temperature Range Small 5mm x 5mm Thin QFN Package Few External Components 1% Threshold Accuracy
Features
Pin-Selectable or User-Adjustable Voltage Detector Thresholds
MAX6892/MAX6893/MAX6894
Ordering Information
PART MAX6892ETJ MAX6893ETI MAX6894ETI TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 32 Thin QFN 28 Thin QFN 28 Thin QFN PKG CODE T3255-4 T2855-8 T2855-8
Pin Configurations
PG1 WDI
TOP VIEW
IN1
IN2
IN3
IN4
32 PG2 PG3 PG4 GND PG5 PG6 PG7 PG8 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
IN5
25 24 23 22 21 IN7 IN8 DBP VCC ENABLE SRT SWT TH4
Applications
Telecommunication/Central Office Systems Networking Systems Servers/Workstations Base Stations Storage Equipment Multimicroprocessor/Voltage Systems
MAX6892
IN6
20 19 18 17 16
*EXPOSED PADDLE
10
11
12
13
14
15
RESET
WDO
MARGIN
TH0
MR
TH1
TH2
Typical Operating Circuit appears at end of data sheet.
THIN QFN
*EXPOSED PAD INTERNALLY CONNECTED TO GND.
Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
TH3
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.) PG_, RESET, WDO .................................................-0.3V to +14V IN1-IN8, TH0-TH4, ENABLE, WDI, MR, MARGIN, SRT, SWT, VCC .....................................................-0.3V to +6V DBP ..........................................................................-0.3V to +3V Input/Output Current (all pins)..........................................20mA Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN (derate 21.3mW/C above +70C).............................................................1702mW 32-Pin Thin QFN (derate 21.3mW/C above +70C)............................................................1702mW Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN1 = VIN6-VIN8 = GND, VIN2-VIN5 = 2.7V to 5.5V, WDI = ENABLE = GND, TH0-TH4 = MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1 and 2)
PARAMETER Operating Voltage Range (Note 3) Undervoltage Lockout Digital Bypass Voltage Supply Current VUVLO VDBP ICC VTH VTH-HYS VTH/C IN1, IN6-IN8 Input Leakage Current IIN -50 IN2-IN5 set as adjustable thresholds For IN_ voltages < the highest IN_ supply or < VCC and thresholds are not set as adjustable VCC VUVLO IN_ falling/rising, 100mV overdrive 5.625 VSRT = VCC CSRT = 47nF VSRT = GND 180 135 180 25 6.25 200 207 230 6.875 220 280 280 290 400 555 3 k ms s ms ms ms nA +50 nA SYMBOL CONDITIONS Voltage on either one of IN2-IN5 or VCC that guarantees the part is fully operational For 1V < (VIN2-VIN5 or VCC ) < VUVLO, PG_ are pulled down to GND with a 10A current No load VIN2 = 5.5V, VIN1, VIN3-VIN8 = GND, no load IN1-IN8, IN_ falling TA = +25C to +85C TA = -40C to +85C -1 -2 0.3 10 MIN 2.7 TYP MAX 5.5 UNITS V
2.5 2.48 2.55 0.9 2.67 1.1 +1
V V mA
Threshold Accuracy (Table 2) Threshold Hysteresis Threshold Tempco
% VTH +2 % VTH ppm/C
IN2-IN5 Input Impedance Power-Up Delay IN_ to PG_ Delay PG_ Timeout Period RESET Default Timeout Period RESET Adjustable Timeout Period SRT Adjustable Timeout Current
RIN2-IN5 tD-PO tD-R tPG tRP tRP-ADJ ISRT
2
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Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN6-VIN8 = GND, VIN2-VIN5 = 2.7V to 5.5V, WDI = ENABLE = GND, TH0-TH4 = MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1 and 2)
PARAMETER SRT Default Timeout Threshold SRT Adjustable Timeout Threshold SRT Adjustable Timeout Discharge Threshold SRT Adjustable Timeout Output Low Discharge Current PG_, RESET, WDO Output Low PG_, RESET, WDO Output Initial Pulldown Current PG_, RESET, WDO Output OpenDrain Leakage Current MR, MARGIN, ENABLE, TH0-TH4, WDI Input Voltage MR Input Pulse Width MR Glitch Rejection MR to RESET Delay MR to DBP Pullup Current MARGIN to DBP Pullup Current ENABLE to PG_ Delay ENABLE Pulldown Current tD-MR I MR IMARGIN tD-ENPG V ENABLE = 0.6V 5 V MR = 1.4V V MARGIN = 1.4V 5 5 SYMBOL VSRT-DEF VSRT-ADJ VSRT-DIS CONDITIONS VSRT VSRT-DEF, selects reset default timeout (Note 4) (Note 5) MIN 1.1 0.95 TYP 1.25 1.0 100 MAX 1.5 1.05 UNITS V V mV
MAX6892/MAX6893/MAX6894
ISRT-DIS VOL IUV
VSRT = 0.3V ISINK = 4mA, output asserted VCC < VUVLO, VPG_, RESET, WDO = 0.8V
0.7 0.4 10 40
mA V A
ILKG VIL VIH T MR
Output high impedance
-1
+1 0.6
A
1.4 1 100 2 10 10 200 10 15 15 15
V
s ns s A A ns A
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3
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN6-VIN8 = GND, VIN2-VIN5 = 2.7V to 5.5V, WDI = ENABLE = GND, TH0-TH4 = MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1 and 2)
PARAMETER TH0-TH4 Input Current WDI Pulldown Current WDI Input Pulse Width Watchdog Default Timeout Period Watchdog Adjustable Timeout Period SWT Adjustable Timeout Current SWT Default Timeout Threshold SWT Adjustable Timeout Threshold SWT Adjustable Timeout Discharge Threshold SWT Adjustable Timeout Output Low Discharge Current tWD tWD-ADJ ISWT VSWT-DEF VSWT-ADJ VSWT-DIS ISWT-DIS VSWT = VCC CSWT = 0.33F VSWT = GND VSWT VSWT-DEF, selects watchdog default timeout period (Note 4) (Note 5) VSWT = 0.3V 0.7 Initial mode Normal mode Initial mode Normal mode IWDI VWDI = 0.6V SYMBOL CONDITIONS MIN -1 5 50 92.16 1.44 53.7 0.93 180 1.1 0.95 102.4 1.6 82.5 1.43 230 1.25 1.0 100 112.64 1.76 111.9 1.94 280 1.5 1.05 s nA V V mV mA 10 TYP MAX +1 15 UNITS A A ns s
Note 1: Note 2: Note 3: Note 4: Note 5:
100% production tested at TA = +25C and TA = +85C. Specifications at TA = -40C are guaranteed by design. Device may be supplied from any one of IN2-IN5, or VCC. The internal supply voltage, measured at VCC, equals the maximum of IN2-IN5. External capacitor is charged by IS_T when VS_T-DIS < VS_T < VS_T-ADJ. External capacitor is discharged by IS_T-DIS down to VS_T-DIS after VS_T reaches VS_T-ADJ.
4
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Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
Typical Operating Characteristics
(VIN1 = VIN6-VIN8 = GND, VIN2-VIN5 = 2.7V to 5.5V, WDI = GND, TH0-TH4 = MARGIN = MR = DBP. Typical values are at TA = +25C.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (IN2-IN5)
MAX6892 toc01
SUPPLY CURRENT vs. SUPPLY VOLTAGE (VCC)
MAX6892 toc02
NORMALIZED PG_ TIMEOUT PERIOD vs. TEMPERATURE
NORMALIZED PG_ TIMEOUT PERIOD
MAX6892 toc03
1.1 1.0 SUPPLY CURRENT (mA) 0.9 0.8 0.7 0.6 0.5 2.5 3.0 3.5 4.0 4.5 5.0 TA = -40C TA = +25C
1.1 1.0 SUPPLY CURRENT (mA) 0.9 TA = +85C 0.8 0.7 0.6 0.5 TA = +25C
1.3 1.2 1.1 1.0 0.9 0.8 0.7
TA = +85C
TA = -40C
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
IN_TO PG_ PROPAGATION DELAY vs. TEMPERATURE
MAX6892 toc04
NORMALIZED DEFAULT RESET TIMEOUT PERIOD vs. TEMPERATURE
MAX6892 toc05
NORMALIZED ADJUSTABLE RESET TIMEOUT PERIOD vs. TEMPERATURE
NORMALIZED RESET TIMEOUT PERIOD 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 85 -40 -15 10 35 tRP = 200ms CSRT = 47nF 60 85
MAX6892 toc06
30 IN_TO PG_ PROPAGATION DELAY (s) 28 26 24 22 20 18 16 14 12 10 -40 -15 10 35 60 100mV OVERDRIVE
1.020 NORMALIZED RESET TIMEOUT PERIOD 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 -40 -15 10 35 tRP = 200ms VSRT = VCC 60
1.10
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
NORMALIZED DEFAULT WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE
MAX6892 toc07
NORMALIZED ADJUSTABLE WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE
NORMALIZED WATCHDOG TIMEOUT PERIOD
MAX6892 toc08
NORMALIZED IN_ THRESHOLD vs. TEMPERATURE
1.004 NORMALIZED IN_ THRESHOLD 1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995
MAX6892 toc09
1.04 NORMALIZED WATCHDOG TIMEOUT PERIOD 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 -40 -15 10 35 60 tRP = 1.6s VSWT = VCC
1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 -40 -15 10 35 tRP = 1.6s CSWT = 0.33F 60
1.005
85
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
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5
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
Typical Operating Characteristics (continued)
(VIN1 = VIN6-VIN8 = GND, VIN2-VIN5 = 2.7V to 5.5V, WDI = GND, TH0-TH4 = MARGIN = MR = DBP. Typical values are at TA = +25C.)
MAXIMUM IN_ TRANSIENT vs. IN_ THRESHOLD OVERDRIVE
MAX6892 toc10
OUTPUT VOLTAGE LOW vs. SINK CURRENT
450 400 350 VOL (mV)
MAX6892 toc11
200 MAXIMUM TRANSIENT DURATION (s) 175 150 125 100 75 50 25 0 1 10 100 PG_ ASSERTION OCCURS
500
300 250 200 150 100 50 0
1000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ISINK (mA)
IN_ THRESHOLD OVERDRIVE (mV)
MR TO RESET PROPAGATION DELAY vs. TEMPERATURE
MAX6892 toc12
RESET TIMEOUT PERIOD vs. CSRT
MAX6892 toc13
2.20 MR TO RESET PROPAGATION DELAY (ns) 2.15 2.10 2.05 2.00 1.95 1.90
10,000
1000 TIMEOUT PERIOD (ms)
100
10
1 1.85 1.80 -40 -15 10 35 60 85 TEMPERATURE (C) 0.1 0.1 1 10 CSRT (nF) 100 1000
WATCHDOG TIMEOUT PERIOD vs. CSWT
MAX6892 toc14
10,000
1000 TIMEOUT PERIOD (ms)
100
10
1
0.1 0.1 1 10 CSWT (nF) 100 1000
6
_______________________________________________________________________________________
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
Pin Description
PIN MAX6892 1 MAX6893 1 MAX6894 1 NAME FUNCTION Open-Drain, Power-Good Output 2. PG2 asserts low when the voltage input at IN2 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG2 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Power-Good Output 3. PG3 asserts low when the voltage input at IN3 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG3 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Power-Good Output 4. PG4 asserts low when the voltage input at IN4 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG4 deasserts with a factory preset timeout period of 6.25ms. Ground Open-Drain, Power-Good Output 5. PG5 asserts low when the voltage input at IN5 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG5 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Power-Good Output 6. PG6 asserts low when the voltage input at IN6 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG6 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Power-Good Output 7. PG7 asserts low when the voltage input at IN7 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG7 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Power-Good Output 8. PG8 asserts low when the voltage input at IN8 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG8 deasserts with a factory preset timeout period of 6.25ms. Open-Drain, Active-Low Reset Output Stage. RESET asserts low when any monitored input (IN_) is below the selected threshold or manual reset (MR) is pulled low. RESET remains low for the reset timeout period after all resetcausing conditions are cleared, and then deasserts. Open-Drain, Active-Low Watchdog Output Stage. If WDI remains high or low for longer than the watchdog timeout period, the internal watchdog timer runs out and the WDO output asserts low. The internal watchdog timer clears whenever RESET is asserted or WDI sees a rising or falling edge. Connect WDO to MR to automatically assert the RESET output after each watchdog timeout fault. Margin Input. MARGIN holds PG_, RESET, and WDO in their existing states when driven low. Leave MARGIN unconnected or connect to DBP if unused. MARGIN overrides MR if both assert at the same time. MARGIN is internally pulled up to DBP through a 10A current source. Active-Low Manual Reset Input. Pull MR low to assert RESET. RESET remains asserted for its preset/adjustable reset timeout period when MR is driven/pulled high. MR is internally pulled up to DBP through a 10A current source. Threshold Selection Input 0. Logic input to select desired thresholds. Connect TH0 to GND or DBP. See Table 2 for available thresholds. Input has no internal pullup or pulldown.
MAX6892/MAX6893/MAX6894
PG2
2
2
2
PG3
3 4 5
3 4 5
3 4 --
PG4 GND PG5
6
6
--
PG6
7
--
--
PG7
8
--
--
PG8
9
7
7
RESET
10
8
8
WDO
11
9
9
MARGIN
12
10
10
MR
13
11
11
TH0
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7
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
Pin Description (continued)
PIN MAX6892 14 MAX6893 12 MAX6894 12 NAME FUNCTION Threshold Selection Input 1. Logic input to select desired thresholds. Connect TH1 to GND or DBP. See Table 2 for available thresholds. Input has no internal pullup or pulldown. Threshold Selection Input 2. Logic input to select desired thresholds. Connect TH2 to GND or DBP. See Table 2 for available thresholds. Input has no internal pullup or pulldown. Threshold Selection Input 3. Logic input to select desired thresholds. Connect TH3 to GND or DBP. See Table 2 for available thresholds. Input has no internal pullup or pulldown. Threshold Selection Input 4. Logic input to select desired thresholds. Connect TH4 to GND or DBP. See Table 2 for available thresholds. Input has no internal pullup or pulldown. Watchdog Timeout Adjust Input. Connect SWT to VCC to select the default watchdog timeout period. Connect an external capacitor between SWT and GND to adjust the watchdog timeout period. The adjustable timeout period is calculated by tWP = 4.348E6 x CSWT (tWP in seconds and CSWT in Farads). Disable the watchdog timer by connecting SWT to GND. Reset Timeout Adjust Input. Connect SRT to VCC to select the default reset timeout period. Connect an external capacitor between SRT and GND to adjust the reset timeout period. The adjustable timeout period is calculated by tRP = 4.348E6 x CSWT (tRP in seconds and CSRT in Farads). Active-Low, PG_ Enable Input. Pull ENABLE high to force all PG_ outputs low. PG_ outputs remain asserted for their timeout period when ENABLE is driven/pulled low. ENABLE is internally pulled down to GND through a 10A current sink. Internal Supply Voltage. Bypass VCC to GND with a 1F capacitor as close to the device as possible. VCC supplies power to the internal circuitry. VCC is internally powered from the highest of the monitored IN2-IN5 voltages. Do not use VCC to supply power to external circuitry. To externally supply VCC, see the Powering the MAX6892/MAX6893/MAX6894 section). Digital Bypass Voltage. DBP supplies power to the output stages. Bypass DBP to GND with a 1F capacitor as close to the device as possible. Do not use DBP to supply power to external circuitry. Input Voltage 8. Select undervoltage threshold using TH0-TH4. See Table 2. For improved noise immunity, bypass IN8 to GND with a 0.1F capacitor as close to the device as possible. Input Voltage 7. Select undervoltage threshold using TH0-TH4. See Table 2. For improved noise immunity, bypass IN7 to GND with a 0.1F capacitor as close to the device as possible.
TH1
15
13
13
TH2
16
14
14
TH3
17
15
15
TH4
18
16
16
SWT
19
17
17
SRT
20
18
18
ENABLE
21
19
19
VCC
22
20
20
DBP
23
--
--
IN8
24
--
--
IN7
8
_______________________________________________________________________________________
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
Pin Description (continued)
PIN MAX6892 25 MAX6893 21 MAX6894 -- NAME FUNCTION Input Voltage 6. Select undervoltage threshold using TH0-TH4. See Table 2. For improved noise immunity, bypass IN6 to GND with a 0.1F capacitor as close to the device as possible. Input Voltage 5. Select undervoltage threshold using TH0-TH4. See Table 2. Power the device through IN2-IN5 or VCC (see the Powering the MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass IN5 to GND with a 0.1F capacitor as close to the device as possible. Input Voltage 4. Select undervoltage threshold using TH0-TH4. See Table 2. Power the device through IN2-IN5 or VCC (see the Powering the MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass IN4 to GND with a 0.1F capacitor as close to the device as possible. Input Voltage 3. Select undervoltage threshold using TH0-TH4. See Table 2. Power the device through IN2-IN5 or VCC (see the Powering the MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass IN3 to GND with a 0.1F capacitor as close to the device as possible. Input Voltage 2. Select undervoltage threshold using TH0-TH4. See Table 2. Power the device through IN2-IN5 or VCC (see the Powering the MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass IN2 to GND with a 0.1F capacitor as close to the device as possible. Input Voltage 1. Select undervoltage threshold using TH0-TH4. See Table 2. For improved noise immunity, bypass IN1 to GND with a 0.1F capacitor as close to the device as possible. Watchdog Timer Input. Logic input for the watchdog timer function. If WDI is not strobed with a valid low-to-high or high-to-low transition within the watchdog timeout period, the watchdog output asserts low. The watchdog timeout period is externally adjustable with capacitor CSWT or selectable for a fixed internal timeout period. The watchdog has a long timeout period (92.16s minimum fixed or 64x the adjusted short timeout period) after each reset event and a short timeout period (1.44s minimum or an adjusted timeout period) after the first valid WDI transition. Open-Drain, Power-Good Output 1. PG1 asserts low when the voltage input at IN1 is below the pin-selectable/adjustable input threshold or ENABLE is pulled high. PG1 deasserts with a factory preset timeout period of 6.25ms. No Connection. Not internally connected. Exposed Paddle. Internally connected to GND. Connect EP to GND or leave floating.
MAX6892/MAX6893/MAX6894
IN6
26
22
--
IN5
27
23
23
IN4
28
24
24
IN3
29
25
25
IN2
30
26
26
IN1
31
27
27
WDI
32 -- EP
28 -- EP
28 5, 6, 21, 22 EP
PG1 N.C. GND
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9
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
Functional Diagram
MARGIN ENABLE
IN2
IN_ DETECTOR PG_ OUTPUT
WOI
MR
OPEN-DRAIN ACTIVE-LOW PG1 10A POWER-UP PULLDOWN
VREF
SWT
IN1 IN3 IN4 IN5* IN6* IN7** IN8**
IN2 DETECTOR IN3 DETECTOR IN4 DETECTOR IN5 DETECTOR IN6 DETECTOR IN7 DETECTOR IN8 DETECTOR
LOGIC ARRAY
DBP
SRT
PG2 OUTPUT PG3 OUTPUT PG4 OUTPUT PG5 OUTPUT PG6 OUTPUT PG7 OUTPUT
DBP
PG2 PG3 PG4 PG5* PG6* PG7** PG8 WDO RESET TH0 TH1 THRESHOLD SELECTION LOGIC
(VIRTUAL DIODES) 2.55V LDO DBP 1F VCC 1F
PG8 OUTPUT WDO OUTPUT RESET OUTPUT
MAX6892 MAX6893 MAX6894
TH2 TH3 TH4
GND
* FOR MAX6892/MAX6893 ONLY. ** FOR MAX6892 ONLY.
10
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Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
Detailed Description
The MAX6892/MAX6893/MAX6894 pin-selectable, multivoltage supply sequencers/supervisors monitor several voltage detector inputs and one watchdog input, asserting the outputs when the respective input thresholds have been reached or a timeout occurs. All versions have an enable manual reset and margin input disable. The MAX6892/MAX6893/MAX6894 voltage thresholds are selected by logic inputs and/or an external voltage-divider. A RESET output ensures all monitored inputs are above the pin-selected/adjustable thresholds. Watchdog and reset timeout periods can use factory default settings or are independently adjustable by connecting external capacitors. In addition, all devices can be powered through the voltage detector inputs alone, or externally supplied from a constant supply on the VCC pin (see the Powering the MAX6892/MAX6893/MAX6894 section). The outputs are factory configured as open drain. The MAX6892/MAX6893/MAX6894 also generate a digital supply voltage (DBP) for the internal logic circuitry and the output stages. Bypass DBP to GND with a 1F ceramic capacitor installed as close to the device as possible. The nominal DBP output voltage is 2.55V. Do not use DBP to provide power to external circuitry.
MAX6892/MAX6893/MAX6894
Inputs
The MAX6892/MAX6893/MAX6894 contain multiple logic and voltage detector inputs. Each voltage detector input is monitored for undervoltage thresholds. Voltage Detector Inputs (IN_) The MAX6892/MAX6893/MAX6894 offer several monitor options with both pin-selectable and adjustable reset thresholds. The threshold voltage at each adjustable IN_ input is typically 0.6V. To monitor a voltage >0.6V, connect a resistor-divider network to the circuit as shown in Figure 1: VIN_TH = VTH (R1 + R2) / R2 (Equation 1) where VIN_TH is the desired reset threshold voltage for the respective IN_ and V TH is the input threshold (0.6V). Resistors R1 and R2 can have high values to minimize current consumption due to low-leakage currents. Set R2 to some conveniently high value (10k, for example) and calculate R 1 based on the desired reset threshold voltage, using the following formula: R1 = R2 x (VIN_TH/VTH - 1)
Powering the MAX6892/MAX6893/MAX6894
The MAX6892/MAX6893/MAX6894 derive power from the voltage detector inputs: IN2-IN5 (MAX6892/ MAX6893), IN2-IN4 (MAX6894), or through an externally supplied VCC. A virtual diode-ORing scheme selects the positive input that supplies power to the device (see the Functional Diagram). The highest input voltage on IN2-IN5 (MAX6892/MAX6893)/IN2-IN4 (MAX6894) supplies power to the device. One of IN2-IN5 (MAX6889/MAX6890)/IN2-IN4 (MAX6891) or VCC must be at least 2.7V to ensure proper operation. Internal hysteresis ensures that the supply input that initially powered the device continues to power the device when multiple input voltages are within 50mV of each other. VCC powers the analog circuitry and is the bypass connection for the MAX6892/MAX6893/MAX6894 internal supply. Bypass VCC to GND with a 1F ceramic capacitor installed as close to the device as possible. The internal supply voltage, measured at VCC, equals the maximum of IN2-IN5. If VCC is externally supplied, VCC must be at least 200mV higher than any voltage applied to IN2-IN5 and VCC must be brought up first. VCC always powers the device when all IN_ are factory set as "ADJ." Do not use the internally generated VCC to provide power to external circuitry.
VIN_TH
R1 IN_ R2 GND MAX6892 MAX6893 MAX6894 VCC
VCC
VIN_TH = 0.6 x (R1 + R2) / R2
Figure 1. Adjusting the Monitored Threshold
______________________________________________________________________________________
11
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
Threshold Logic Inputs (TH0-TH4) The TH0-TH4 logic inputs select the undervoltage thresholds and tolerance of the IN1-IN8 inputs (MAX6892), IN1-IN6 inputs (MAX6893), and IN1-IN4 inputs (MAX6894). TH0-TH4 define 32 unique options for the supervisor functionality. Connect the respective TH_ to GND for a logic 0 or to DBP for a logic 1. Tables 1 and 2 show the 32 unique threshold options available. TH4 sets the threshold tolerance of the undervoltage threshold. A logic 1 selects a 5% supply tolerance and a logic 0 selects 10% supply tolerance. The MAX6892/MAX6893/ MAX6894 logic determines which thresholds should be used for the IN inputs only at power-up. Use the voltagedivider circuit of Figure 1 and Equation 1 to set the threshold for the user-adjustable inputs as described in the Voltage Detector Inputs (IN_) section.
Table 1. Nominal Monitored Supply Voltages
SELECTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TH4-TH0 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 MONITORED SUPPLY VOLTAGES (V) IN1 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ IN2 5 5 5 5 5 5 5 5 3.3 3 3.3 3 3.3 3 3.3 3 5 5 5 5 5 5 5 5 3.3 3 3.3 3 3.3 3 3.3 ADJ IN3 3.3 3 3.3 3 3.3 3 3.3 3 2.5 2.5 2.5 2.5 1.8 1.8 2.5 2.5 3.3 3 3.3 3 3.3 3 3.3 3 2.5 2.5 2.5 2.5 1.8 1.8 2.5 ADJ IN4 2.5 2.5 2.5 2.5 1.8 1.8 ADJ ADJ 1.8 1.8 ADJ ADJ ADJ ADJ 1.8 1.8 2.5 2.5 2.5 2.5 1.8 1.8 ADJ ADJ 1.8 1.8 ADJ ADJ ADJ ADJ 1.8 ADJ IN5 1.8 1.8 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 1.5 1.5 1.8 1.8 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ 1.5 ADJ IN6 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ IN7 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ IN8 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ SUPPLY TOLERANCE (%) 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 --
12
______________________________________________________________________________________
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
Table 2. Threshold Options
SELECTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TH4-TH0* 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 THRESHOLD VOLTAGES (V) IN1 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 IN2 4.62 4.62 4.62 4.62 4.62 4.62 4.62 4.62 3.06 2.78 3.06 2.78 3.06 2.78 3.06 2.78 4.38 4.38 4.38 4.38 4.38 4.38 4.38 4.38 2.88 2.62 2.88 2.62 2.88 2.62 2.88 0.60 IN3 3.06 2.78 3.06 2.78 3.06 2.78 3.06 2.78 2.31 2.31 2.31 2.31 1.67 1.67 2.31 2.31 2.88 2.62 2.88 2.62 2.88 2.62 2.88 2.62 2.19 2.19 2.19 2.19 1.58 1.58 2.19 0.60 IN4 2.31 2.31 2.31 2.31 1.67 1.67 0.60 0.60 1.8 1.8 0.60 0.60 0.60 0.60 1.67 1.67 2.19 2.19 2.19 2.19 1.58 1.58 0.60 0.60 1.8 1.8 0.60 0.60 0.60 0.60 1.58 0.60 IN5 1.67 1.67 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 1.39 1.39 1.58 1.58 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 1.31 0.60 IN6 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 IN7 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 IN8 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60 0.60
*TH4 = `1' selects 7.5% threshold tolerance, TH4= `0' selects 12.5% threshold tolerance. Contact factory for alternative thresholds.
______________________________________________________________________________________
13
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
Watchdog Timer The MAX6892/MAX6893/MAX6894s' watchdog circuit monitors the microprocessor's (P's) activity. If the P does not toggle the watchdog input (WDI) within the watchdog timeout period, the watchdog output (WDO) asserts. The internal watchdog timer is cleared by RESET, or by a transition at WDI (which can detect pulses as short as 50ns). The watchdog timer remains cleared while reset is asserted. The timer starts counting as soon as WDO is released (see Figure 2). The MAX6892/MAX6893/MAX6894 feature two modes of watchdog timer operation: normal mode and initial mode. At power-up, after a reset event, or after the watchdog timer expires, the initial watchdog timeout is active. After the first transition on WDI, the normal watchdog timeout is active. The initial and normal watchdog timeouts are determined by the value of the capacitor connected between SWT and ground or by connecting SWT to VCC (see the Selecting the Reset and Watchdog Timeout Capacitor section). The initial watchdog timeout is approximately 64 times the normal watchdog timeout. For example, in initial mode a 1F capacitor gives a watchdog timeout period of about 5min. If WDO is connected to MR, the WDO asserts for a short duration (~5s), long enough to assert the RESET output. Asserting RESET clears the watchdog timer and WDO goes high. The reset output remains asserted for its timeout period after a watchdog fault. The watchdog timer stays cleared as long as RESET is low. The watchdog timeout period is determined by the value of the capacitor connected between SWT and ground (see the Selecting the Reset/Watchdog Timeout Capacitor section). Connect SWT to DBP to select factory-programmed watchdog timeout. To disable the watchdog timer connect SWT to GND.
2.5V VCC OR IN2-IN5 WDO
RESET
WDI tD-PO 2.5V VCC OR IN2-IN5 WDO tRP *tWDI tWD WDO NOT CONNECTED TO MR *tWDI
RESET
WDI tD-PO tRP *tWDI tWD WDO CONNECTED TO MR. tRP *tWDI
*tWDI IS THE INITIAL WATCHDOG TIMEOUT PERIOD.
Figure 2. Watchdog, Reset, and Power-Up Timing Diagram
14
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Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
Manual Reset (MR) Many P-based products require manual reset capability to allow an operator or external logic circuitry to initiate a reset. The manual reset input (MR) can connect directly to a switch without an external pullup resistor or debouncing network. MR is internally pulled up to DBP through a 10A current source and, therefore, can be left unconnected if unused. MR is designed to reject fast falling transients (typically 100ns pulses) and it must be held low for a minimum of 1s to assert RESET. After MR transitions from low to high, RESET remains asserted for the duration of the reset timeout period. Margin Output Disable (MARGIN) MARGIN allows system-level testing while power supplies exceed the normal ranges. Driving MARGIN low forces PG_, RESET, and WDO to hold the last state while system-level testing occurs. Leave MARGIN unconnected or connect to DBP if unused. An internal 10A current source pulls MARGIN to DBP. The state of each programmable output, RESET, and WDO does not change while MARGIN = GND. Enable Input ENABLE is an active-high, logic input. Driving ENABLE high pulls all PG_ low. Drive ENABLE high or leave floating for normal operation. ENABLE is internally pulled down to GND through a 10A current sink. RESET changes from high to low whenever one or more input voltage (IN1-IN8) monitors drop below their respective reset threshold voltage or when MR is pulled low for a minimum of 1s. Once the affected input voltage monitor(s) exceeds its respective reset threshold voltage(s), RESET remains low for the reset timeout period, then deaaserts.
MAX6892/MAX6893/MAX6894
Applications Information
Selecting the Reset/Watchdog Timeout Capacitor
The reset timeout period can be adjusted to accommodate a variety of P applications. Adjust the reset timeout period (t RP ) by connecting a capacitor (CSRT ) between SRT and ground. Calculate the reset timeout capacitor as follows: CSRT = tRP / (4.348 x 106) with tRP in seconds and CSRT in Farads. Connect SRT to V CC for a factory-programmed reset timeout of 200ms (typ). The watchdog timeout period can be adjusted to accommodate a variety of P applications. With this feature, the watchdog timeout can be optimized for software execution. The programmer can determine how often the watchdog timer should be serviced. Adjust the watchdog timeout period (tWD) by connecting a specific value capacitor (C SWT) between SWT and GND. For normal mode operation, calculate the watchdog timeout capacitor as follows: CSWT = tWD / (4.348 x 106) with tWD in seconds and CSWT in Farads. Connect SWT to VCC for a factory-programmed watchdog timeout of 1.6s (normal mode) and 102.4s (initial mode). CSRT and CSWT must be a low-leakage (<10nA) type capacitor. Ceramic capacitors are recommended.
Power-Good Outputs
The MAX6892 features eight power-good outputs, the MAX6893 features six power-good outputs, and the MAX6894 features four power-good outputs. Each output (PG_) responds to its respective input (IN_). Each PG_ is open drain. During power-up, the outputs pull down to GND with an internal 10A current sink for 1V < VCC < VUVLO.
RESET Output
The reset output is typically connected to the reset input of a P. A P's reset input starts or restarts the P in a known state. The MAX6892/MAX6893/MAX6894 supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power-down, and brownout conditions.
Layout and Bypassing
For better noise immunity, bypass each of the voltage detector inputs to GND with 0.1F capacitors installed as close to the device as possible. Bypass VCC and DBP to GND with 1F capacitors installed as close to the device as possible.
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15
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
Pin Configuration (continued)
PG1
WDI
PG1
IN2
28
PG2 PG3 PG4 GND PG5 PG6 RESET
27
26
25
24
23
22 21 20 19
IN6 DBP VCC ENABLE SRT SWT TH4 PG2 PG3 PG4 GND N.C. N.C. RESET
28 1 2 3 4 5 6 7 8
WDO
27
26
25
24
IN3
23
1 2 3 4 5 6 7 8
WDO
N.C.
WDI
TOP VIEW
IN1
IN4
IN2
IN3
IN5
TOP VIEW
IN1
IN4
22 21 20 19
N.C. DBP VCC ENABLE SRT SWT TH4
MAX6893
18 17
MAX6894
18 17
*EXPOSED PADDLE
16 15
*EXPOSED PADDLE
16 15
9
MARGIN
10
MR
11
TH0
12
TH1
13
TH2
14
TH3
9
MARGIN
10
MR
11
TH0
12
TH1
13
TH2
14
TH3
THIN QFN
*EXPOSED PAD INTERNALLY CONNECTED TO GND.
THIN QFN
*EXPOSED PAD INTERNALLY CONNECTED TO GND.
Chip Information
PROCESS: BiCMOS
16
______________________________________________________________________________________
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
Typical Operating Circuit
5V DC-DC 1 5V 3.3V
MAX6892/MAX6893/MAX6894
DC-DC 2
2.5V DC-DC 3 1.8V DC-DC 4 1.5V
VCC
IN1 IN2
PG2
IN3
PG3
IN4
PG4
IN5
PG5
IN6 RESET WDI RESET
P
LOGIC OUTPUT LOGIC INPUT
DBP TH0 TH1 TH2 TH3 TH4 ENABLE SRT CSRT SWT CSWT PG1 PG6 GND
WDO
MAX6893
MARGIN
MR
5V SUPPLY PG2 3.3V SUPPLY PG3 2.5V SUPPLY PG4 1.8V SUPPLY PG5 1.5V SUPPLY RESET tPG2
5V BUS INPUT ENABLE 3.3V DC-DC CONVERTER 3.3V OUTPUT tPG3 ENABLE 2.5V DC-DC CONVERTER 2.5V OUTPUT tPG4 ENABLE 1.8V DC-DC CONVERTER 1.8V OUTPUT tPG5 ENABLE 1.5V DC-DC CONVERTER 1.5V OUTPUT tRESET
SYSTEM RESET
______________________________________________________________________________________
17
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors MAX6892/MAX6893/MAX6894
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
QFN THIN.EPS
L
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
XXXXX
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
G
1
2
18
______________________________________________________________________________________
Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX6892/MAX6893/MAX6894
COMMON DIMENSIONS PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1
EXPOSED PAD VARIATIONS
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
DOWN BONDS ALLOWED
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 -
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** **
NO YES NO NO YES NO Y NO NO YES YES NO NO YES Y N NO YES NO NO
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
** SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. PACKAGE OUTLINE, 16, 20, 28, 32L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
G
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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